1. Field of the Invention
The present invention relates generally to a semiconductor memory device. More particularly, the invention relates to a phase change memory device having a wordline driving circuit with a reduced layout size.
A claim of priority is made to Korean Patent Application No. 10-2005-0023242 filed on Mar. 21, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Phase change memory devices store data using phase change materials, such as chalcogenide, which are capable of stably transitioning between amorphous and crystalline phases. The amorphous and crystalline phases (or states) exhibit different resistance values, which are used to distinguish different logic states of memory cells in the memory devices. In particular, the amorphous phase exhibits a relatively high resistance, and the crystalline phase exhibits a relatively low resistance.
At least one type of phase change memory device—phase change random access memory (PRAM)—uses the amorphous state to represent a logical ‘1’ and the crystalline state to represent a logical ‘0’. In a PRAM device, the crystalline state is referred to as a “set state”, and the amorphous state is referred to as a “reset state”. Accordingly, a memory cell in a PRAM stores a logical ‘1’ by “setting” a phase change material in the memory cell to the crystalline state, and the memory cell stores a logical ‘0’ by “resetting” the phase change material to the amorphous state. Various PRAM devices are disclosed, for example, in U.S. Pat. Nos. 6,487,113 and 6,480,438.
The phase change material in a PRAM is converted to the amorphous state by heating the material to above a predetermined melting temperature and then quickly cooling the material. The phase change material is converted to the crystalline state by heating the material at another predetermined temperature below the melting temperature for a set period of time. Accordingly, data is written to memory cells in a PRAM by converting the phase change material in memory cells of the PRAM between the amorphous and crystalline states using heating and cooling as described.
The phase change material in a PRAM typically comprises a compound including germanium (Ge), antimony (Sb), and tellurium (Te), i.e., a “GST” compound. The GST compound is well suited for a PRAM because it can quickly transition between the amorphous and crystalline states by heating and cooling.
FIG. 1 illustrates a conventional phase change memory cell “C” of a diode type PRAM. Referring to FIG. 1, memory cell “C” comprises a phase change resistance element GST connected to a bitline BL, and a diode “D” connected between phase change resistance element GST and a wordline WL.
Phase change memory cell “C” is accessed by selecting wordline WL and bitline BL. In order for phase change memory cell “C” to work properly, wordline WL must have a lower voltage level than bitline BL when wordline WL is selected so that current can flow through phase change resistance element GST. Diode “D” is forward biased so that if wordline WL has a higher voltage than bitline BL, no current flows through phase change resistance element GST. To ensure that wordline WL has a lower voltage level than bitline BL, wordline WL is generally connected to ground when selected.
The operation of memory cell “C” is described in further detail below in the context of a conventional phase change memory device.
FIG. 2 is a diagram of a conventional phase change memory device 200. Referring to FIG. 2, phase change memory device 200 comprises a memory cell block CBLK comprising a plurality of phase change memory cells, a wordline driving unit 210, a column selection circuit 220, and a writing driver 230.
Wordline driving unit 210 comprises a plurality of wordline driving circuits for converting address and activation signals into wordline voltages. For simplicity of illustration, FIG. 2, shows only one wordline driving circuit WDC connected to wordline WL0. Other wordline driving circuits in wordline driving unit 210 function similarly to wordline driving circuit WDC, and therefore a further explanation thereof is omitted to avoid redundancy.
Wordline driving circuit WDC receives an address signal ADD and an activation signal EN and generates a signal on wordline WL0. Wordline driving circuit WDC comprises a NOR gate N1 receiving address signal ADD and activation signal EN, and an inverter I1 receiving an output from NOR gate N1 and generating the signal on wordline WL0.
Column selection circuit 220 selects bitlines according to the voltage levels of column selection signals Y0 through Yk. Writing driver 230 supplies a write current to the selected bitlines.
To illustrate the operation of a selected memory cell in memory device 200, it will be assumed that wordline WL0 and bitline BLk are selected. Wordline WL0 is selected by setting activation signal EN and address signal ADD to logical ‘0’ so that the output of NOR gate N1 is a logical ‘1’, causing wordline WL0 to be connected to ground VSS through inverter I1. Bitline BLk is selected by setting column selection signal Yk to logical ‘1’ so that writing driver 230 provides the write current to bitline BLk. The write current flows through bitline BLk to ground VSS through the memory cell and wordline driving circuit WDC, as indicated by a dotted line in FIG. 2.
One shortcoming of memory device 200 is that the wordline driving circuits take up a significant amount of chip space. By occupying so much chip space, the wordline driving circuits limit the number of memory cells that can be formed in memory device 200.